Currently, device density within integrated circuits requires critical dimensions of approximately 0.5 microns and smaller. At these dimensions, chemical-mechanical polishing (CMP) is virtually required for planarizing insulating layers or making conductive plugs. In the prior art, center-to-edge nonuniformity problems occur during CMP. Typically, the polishing rate is less near the center of the wafer compared to the edge of the wafer.
In an attempt to improve the center-to-edge uniformity, a number of different styles of polishing pads have been proposed. Some of these prior pads are in U.S. Pat. Nos. 5,441,598 (Yu) and 5,020,283 (Tuttle). These patents include a changing feature density across the surface of the polishing pad. Even with these different styles of polishing pads, problems with center-to-edge nonuniformity can still exist. Therefore, a need exists to further improve center-to-edge uniformity for CMP processes.